Floating point arithmetic has been built into many computing devices since the 1950's and has often been preferred for many scientific, engineering and financial calculations. In some ways, it has mimicked fixed point or integer arithmetic. The mathematical operations of addition, subtraction, multiplication and division are well supported in traditional floating point literature. The literature is vast, and at this time, nearly static with little fundamental growth being reported.
Fixed point arithmetic has always had some operations which it did much better than floating point. It has long been possible to build fixed point adders of more than two fixed point numbers. It has long been possibly to multiply a fixed point number by a power of two in an adder, merely by shifting the bits of the fixed point number. Neither of these statements are true for floating point arithmetic processors. What is needed are floating point arithmetic processing elements which can add more than two floating point operands, and which can effectively multiply a floating point operand by a power of two, creating a shifted floating point operand.
The use of inexpensive shifting of fixed point numbers in fixed point adders has been used extensively in the development of wavelet filter banks. While fixed point arithmetic is not as good at preserving the precision of small values, it is cheap. New arithmetic processors are needed that are comparably capable of supporting wavelet filter banks.
While it is possible with multiple conventional, floating point adders to add more than two floating point operands together, this is done at a large cost in terms of control, communication, circuitry, power and heat dissipation. Floating point arithmetic processors are needed which minimize both the control and communication overhead for such operations using less circuitry, consuming less power, and dissipating less heat.